1. Field of the Invention
The present invention relates to a board layout check apparatus and a board layout check method for a printed board and, more particularly, to a board layout check apparatus and a board layout check method for checking whether or not guard wirings are appropriately arranged on printed wiring layers on the printed board. The present invention also relates to a computer readable recording medium on which a board layout check program is recorded.
2. Description of Related Art
With an increase in operation frequency of an electronic circuit, a countermeasure against electromagnetic radiated emission of an electronic appliance becomes important. As a measure against noise on a printed board, a method of arranging guard wirings on both the sides of an important wiring or a high-speed signal wiring such as a clock wiring is generally used. The guard wirings are arranged for the clock wiring or the high-speed signal wiring to advantageously reduce influence of noise generated from other wirings and parts. Furthermore, a guard wiring is arranged for the clock wiring or the high-speed signal wiring to make it possible to reduce influence of noise to other wirings, parts, and the like.
A system which checks whether or not a guard wiring is appropriately formed at a necessary place is disclosed in Japanese Unexamined Patent Publication No. 2000-20573. In a board wiring process system disclosed in Japanese Unexamined Patent Publication No. 2000-20573, a wiring pattern for a clock signal is detected to detect whether or not two upper and lower layers of the wiring pattern are wired only by a power supply/ground or a guard wiring is formed next to a wiring. A wiring which does not satisfy design conditions of a guard wiring set in advance on the basis of the detection result is detected as an error wiring.
However, in the board wiring process system in Japanese Unexamined Patent Publication No. 2000-20573, only an error wiring is displayed, and a place required to be corrected or a place which can be corrected is not displayed. Therefore, when a given place where a printed wiring layer is arranged next to a guard wiring and a place different from the given place are mixed, a designer must check a printed wiring layer displayed as an error wiring to find and correct a place where no guard wiring is formed.
Therefore, means which displays places where no guard wirings are formed on a printed board is conceived. However, when a guard wiring is actually formed, depending on an arrangement of part terminals and an interval between the guard wiring and an adjacent printed wiring layer, a place where the guard wiring cannot be physically formed is present. When a board layout check system is applied to the place, the place is determined as an error place. For this reason, the designer must determine again whether or not the error place can be corrected.